Comparing Two Y∆-Based Methodologies for Realizable Model Reduction

From a background of RC interconnect models in layout-to-circuit extraction, this paper compares two realizable model reduction methodologies based on generalized Y∆ transformation. The first method represents admittances through a rational function in the s-domain, where the numerator and denominator polynomials are truncated at a user-defined order. During the Y∆ transformation, common factors in the numerator and denominator are identified and cancelled. The rational form of the admittances allows realization through e.g. Brune synthesis. The second method represents admittances through a moments expansion up to a user-defined order. It also allows synthesis after a Padé matching step. In that sense, the methods are equivalent. Nevertheless, a comparison shows that the former performs better in the frequency